在过去的十年里，电子领域在设备小型化、总功耗降低、系统便携性等方面发生了显著的发展。然而，对于现有的硅基技术，摩尔比例定律正在迅速接近其物理极限。随着器件尺寸的不断减小，漏极诱导势垒降低(DIBL)和VT滚转等短通道效应越来越突出。在探索石墨烯之后，研究者们对单层过渡金属二卤属化合物(TMDs)、hBN等二维层状材料产生了浓厚的兴趣。其中，tmd似乎是解决MOSFET缩放问题的好方法。他们提供良好的静电控制比他们的散装同行。此外，它们是共价键固体，其中相邻的堆叠层由弱范德华力保持。因此，它们可以很容易地剥离成单层，也没有悬空键。在各种tmd中，MoS2 (Molybednum Disulfide)似乎是理想的研究对象，因为它的直接带隙为1.8 eV，高开关电流比和相当好的载流子迁移率。然而，在MoS2晶体管的源/漏端实现低电阻接触是一个非常大的挑战。 This attributes to the low on-current in MoS2. Experimental techniques where local metallic phase is deposited on usual semiconducting MoS2 have attracted lot of attention. In conjunction with the experiments, density functional theory (DFT) based atomistic modeling of metal-2D material interface is important to get insights on the charge transfer through these systems. Therefore in this work, we have used DFT to compare the Schottky barrier height (SBH) of two polytypes of phase engineered MoS2 by calculating their elecronic structures. We also propose a novel asymmetric Au-MoS2-Au atomistic model to assess the carrier transport, estimate the contact resistance values of hetero interface using Non Equilibrium Green’s Function(NEGF) approach. We have shown that the contact resistance of Au-1T0-Au has decreased by three-fold compared to Au-2H-Au device.

研究人员:Richa Chakravarty, ME Micro(2016)。

多栅极(双栅极、三栅极或四栅极)MOSFET是取代传统块状MOSFET的必要器件，以便在未来CMOS缩放过程中不受阻碍。在双栅极器件中，独立双栅极(IDG) MOSFET由于两个栅极终端的独立控制，具有动态调节阈值电压和跨导的能力，从而提供了最大的设计灵活性。因此，开发基于表面势的紧凑模型来准确地描述IDG MOSFET的行为在最近受到了相当大的关注。这项工作旨在解决这一领域的一些潜在问题。基于表面电位的紧凑模型需要从泊松方程中快速准确地求解输入电压方程(称为P-IVEs或Primary IVEs)，以确定源极和漏极端的表面电位值，从而计算晶体管的其他物理参数。对于IDG MOSFET，隐式P-IVEs的鲁棒数值解需要使用根括号方法(rbm)，而不是常用的牛顿-拉弗森(NR)技术，因为P-IVEs中存在不可移动的不连续和奇异性。在这项工作中，对文献中可用的不同RBM进行了详尽的研究，并提出了一种单一的、无导数的RBM (LZ4)，它比先前提出的混合NR-Ridders算法具有更快的收敛速度，以求解IDG MOSFET的三角和双曲P-IVEs。通过对三角函数P-IVE的解空间进行一些调整，进一步减少了计算时间。通过Verilog-A接口和多种电路块的仿真，在商业电路模拟器中实现三角P-IVE后，计算效率提高了约60%，双曲P-IVE提高了约15%。终端费用的精确建模是紧凑模型的重要组成部分。 To overcome the limitations of the traditional charge linearization techniques for IDG MOSFET, a piecewise linearization technique for calculating the terminal charges is necessary. This requires formulating an additional set of IVEs, referred to as the S-IVEs or Secondary IVEs. The S-IVEs help to determine the surface potential at some pre- determined points along the channel. The nature of the Secondary IVEs is investigated here and an efficient solution methodology is proposed. The proposed solution is also implemented in a circuit simulator to compare the solution time with that for the P-IVEs. Although sufficiently accurate in predicting the device behavior in strong inversion, compact models for the IDG MOSFET based on the unipolar Poisson equation solution have a few limitations. These include the inability to accurately model the accumulation and near at band regions of operation. Varactor modeling of the IDG MOSFET also demands a complete solution of the bipolar Poisson equation. Here, we rigourously solve the Bipolar Poisson equation to derive an analytical model involving the Legendre’s incomplete elliptic integral of the rst kind and Jacobian elliptic functions. The proposed model is constructed along similar lines as that for the unipolar Poisson equation solution and it is seen that the device behavior is again governed by different sets of IVEs based on the bias condition. After investigating the solution space for the set of IVEs obtained, we employ the LZ4 RBM to solve the IVEs and obtain the potential profle for various bias conditions. The results thus obtained show good agreement with the numerical solution of the Poisson equation under all bias conditions.

研究人员:Abraham Aby, ME Micro(2012)。

基于单壁碳纳米管(SWCNT)的超大规模集成电路(VLSI)互连是一种新兴技术，有潜力克服即使是先进的铜基互连仍然存在的热问题。这是因为它有很好的电和热输运特性。可以说，由于SWCNTs的准一维性，其热能输运是高度各向异性的，与碳的其他同素异形体一样，声子是热传导的主要能量载体。对于常规互连材料，铜和铝，尽管它们的热导率在低于100 K，接近室温和高于室温的温度下变化了几个数量级，但它们几乎具有恒定的值。另一方面，已报道的悬浮金属SWCNTs的实验研究表明，在低温、室温和高温下，纵向晶格热导率(κ l)随温度(T)和管长(l)有很大变化。基于物理学的金属SWCNT κ l作为l和T的函数的分析公式对于有效量化这一新兴技术对集成电路热管理问题的影响至关重要。在这项工作中，基于物理的金属SWCNTs κ l的直径无关分析模型被认为是l在宽范围t上的函数，金属SWCNTs中的热传导受三种电阻声子散射过程的控制;二阶三声子乌姆克拉普散射、质量差散射和边界散射。本研究考虑了上述所有过程，有效模态依赖的松弛时间由Matthiessen规则确定。利用单模弛豫时间近似下的声子玻尔兹曼输运方程推导非平衡分布函数。 The heat flux as a function of temper- ature gradient is obtained from this non-equilibrium distribution function. Based on the Fourier’s definition of thermal conductivity, κ l of metallic SWCNT is formulated and the Debye approximations are used to arrive at an analytical model. The model developed is validated against both the low and high temperature exper- imental investigations. At low temperatures, thermal resistance of metallic SWCNT is due to phonon-boundary scattering process, while at high temperatures it is governed by three phonon Umklapp scattering process. It is understood that apart from form factor due to mass difference scattering, boundary scattering also plays the key role in determining the peak value. At room temperature, κ l of metallic SWCNT is found to be an order of magnitude higher than that of most of metals. The reason can be attributed to the fact that both sound velocity and Debye temperature which have direct effect on the phonon transport in a solid, are reasonably higher in SWCNTs. Though Umklapp processes reduce the κ l steeper than 1/T beyond room-temperature, it’s magnitude is around 1000 W/m/K upto 800 K for various tube lengths, which confirms that this novel material is indeed an efficient conductor of heat also, at room-temperature and above.

研究人员:A.Rex, M.Sc. Engineering(2011)。

准静态近似假定通道中任何位置的电荷密度随施加电压瞬时变化，即假定通道中的传输时间为零。更具体地说，如果QI = f(VD, VS, VG)(大写下标表示DC量)，QI = f(VD, VS, VG)，其中小写下标表示时变量。然而，由于通道传输时间不是零，基于准静态近似的分析引入了由于MOSFET的分布式特性而快速变化的终端电压的误差。在高频率下，传输时间lvd变得与终端交流电压的时间周期相当，因此在电压和通道电荷对电压的响应之间存在有限的时间滞后。将晶体管的分布特性考虑在内的模型被称为非准静态(NQS)模型。NQS模型的推导不是一项简单的任务，因为它需要同时求解传输方程和连续性方程。这项工作的目的是预测对称双栅极(SDG)和栅极全能(GAA)MOSFET在高频小信号变化和大信号快速瞬变下的行为。在小信号分析的情况下，时间变化可以用j!N，因此，问题简化为解常微分方程。高频分析大多是根据导纳(y)参数进行的，因此小信号分析的目标是观察器件y参数随频率的变化。 For large signal analysis, we have to solve a non linear parabolic partial differential equation. Here the main objective is to derive equations that can accurately predict the terminal currents when an input voltage of rise time sufficiently less than the transit time is applied. The large signal analysis is extremely rigorous and no complete analytical solution exists till date.

研究人员:Sudipta Sarkar, M.E. Micro(2010)。

由于FinFET的自对准工艺步骤和与传统的平面CMOS(互补金属氧化物半导体)技术的兼容性，它已成为在硅晶圆上实现多栅mosfet(金属氧化物半导体场效应晶体管)的最有前途的器件架构。一般的FinFET结构本质上是三栅(TG) MOSFET，可以通过适当缩放氧化层厚度转换为双栅或四栅MOSFET。虽然已经为对称双栅mosfet和非对称/独立双栅mosfet提出了几个分析模型，但尚未报道三栅晶体管的物理模型。这是由于解决二维泊松方程的复杂性，它的右手边有指数非线性。本文建立了TG FinFET反转电荷的解析模型，为建立紧凑模型奠定了基础。从控制二维泊松方程中，严格地表明TG FinFET中的总反转电荷可以分为三个分量:来自组成对称双栅(SDG)的电荷，来自组成独立双栅(IDG)的电荷和来自耦合分量的电荷。结果表明，由SDG和IDG分量产生的反转电荷的解析表达式可以从现有模型中得到，但很难得到耦合项的简化解析表达式。基于一些实际的近似，我们提出了一些建模耦合项的技术。使用这些技术获得的模型在广泛的设备参数范围内的所有操作制度下进行了数值模拟验证。在这一发展中，我们忽略了角效应，因为它是微不足道的非掺体装置。 While deriving the inversion charge model for FinFET, it is observed that previous techniques [Lu and Taur, IEEE Trans. Elec. Dev., Vol. 53,No. 5, 2006, Conde et al., IEEE Trans. Elec. Dev., Vol. 54, No. 1, 2007 and Liu et al., IEEE Trans. Elec. Dev., Vol. 55, No.3, 2008] used for solving the one-dimensional Poisson’s equation rigorously for long channel asymmetric and independent double gate transistor result in potential model that involves multiple inter-coupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This work also reports a different rigorous technique for solving the same Poisson equation by which one can obtain the potential profile of a generalized independent double gate transistor that involves a single implicit equation. Proposed model appears to be much more computationaly efficient for circuit simulation than the previous models.

研究员:Avinash Saho, M.Sc. Engineering(2009)。

基于硅纳米线的多栅金属氧化物场效应晶体管(MG-MOSFET)在45nm后技术节点中取代了传统的块状晶体管。在这种晶体管中，短通道效应(SCE)由器件几何形状控制，因此使用未掺杂(或轻掺杂)超薄体硅纳米线来维持通道。未掺杂体的使用也解决了体mosfet中的几个问题，例如随机掺杂波动、迁移率退化和与中间隙金属栅极的兼容性。这种器件的静电完整性随着本体厚度的减小而增大。由于在超薄体器件中电子能量的量子化是不可忽视的，因此在其阈值电压模型中考虑量子效应是极其重要的。目前报道的大多数模型都适用于长通道双栅极器件。只有Muntenu等人[非结晶固体杂志vol 351 pp 1911-1918 2005]报道了短通道对称双栅MOSFET的阈值电压模型，但它涉及非物理拟合参数。另一方面，除了数值模拟结果外，其他类型mg - mosfet(如三栅极、四栅极、圆柱体)的紧凑建模工作尚未报道。在这项工作中，我们报道了基于物理的闭形式量子阈值电压模型的短通道对称双栅极，四栅极和圆柱体栅极全能mosfet。在这些器件中，量子效应主要是由于电子能量的结构限制。 Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schroedinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated againt the professional numerical simulator.

研究员:P. Rakesh Kumar, M.Sc. Engineering(2009)。

在即将到来的sub-45nm技术节点中，未掺杂体多栅(MG)金属氧化物半导体场效应晶体管(MOSFET)正成为单栅体MOSFET的替代品。因此，为了将其用于纳米级集成电路的设计和仿真，开发紧凑型MG晶体管模型是非常必要的。然而，传统体晶体管的静电性能与非掺杂体器件之间有明显的区别。在块体晶体管中，衬底被充分掺杂，反转电荷位于靠近表面的位置，因此表面电位完全控制器件的静电完整性。而在非掺杂体器件中，栅极电场穿透体中心，反转电荷遍及体内。与体晶体管相比，在弱反转状态下，未掺杂体器件的体中心电位高于表面电位，电流通过器件中心而不是表面，这取决于器件几何形状。一些关键参数(如次阈值斜率)有时更依赖于身体中心的潜力，而不是表面。因此，为了准确计算无掺杂体多门晶体管的反转电荷、阈值电压等相关参数，还需要对体心电位和表面电位进行正确建模。虽然已经提出了几种MG晶体管的潜在模型来捕捉亚阈值状态下的短通道行为，但大多数模型都是基于将二维泊松方程转换为拉普拉斯方程的关键近似。这种近似只在表面有效，但在中心和适度反演情况下失效。 As a result all the previous models fail to capture the potential of body center correctly and remain valid only in weak-inversion regime. In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.

研究人员:Biswajit Ray, M.Sc. engineering(2008)。

互连构成了现代芯片设计中电路延迟的主要来源。随着技术规模的不断扩大，芯片互连也在缩小。现代VLSI技术中关键尺寸的变化导致了互连性能的变化，在时间验证中必须充分考虑到这一点。然而，处理大量的模间/模内变化并评估它们对电路性能的影响会极大地复杂化时序分析。在本文中，提出了一种实用的互连延迟变分分析技术，以方便有效地评估导线性能的变异性。通过将随机系数的电报方程转化为随机微分方程，建立了互连过程变异性的模型。我们测量了这种转换如何准确地将进程变化映射到输出延迟的可变性。随后，我们提出了一种新颖而有效的算法，用于在过程变化的情况下对互连网络进行建模。我们开发了一种考虑高斯金属工艺变化影响的互连延迟分析方法。将分布式RC线路的电阻和电容表示为独立的高斯随机变量，然后用它们来计算互连网络中所有节点的延迟概率分布函数的标准差。 We validate the accuracy of our approach against SPICE based Monte Carlo simulations while having greatly lowered the computational cost.

研究人员:Sivakumar Bondada, M.E. Micro(2008)。

隧道场效应晶体管(TFET)具有低于60mv /decade的亚阈值斜率和极高的离子/IOFF比，在电池寿命非常重要的低待机功率(LSTP)应用中引起了足够的关注。到目前为止，这方面的研究还局限于数值模拟和实验分析。然而，为了在纳米级集成电路设计和仿真中应用，开发紧凑的TFET模型是非常必要的。在这项工作中，我们首次建立了n通道双栅TFET (nDGTFET)的解析次阈值斜率模型。与传统的fet不同，TFET中的电流主要由源/通道接口的带对带隧道机制控制。由于总漏极电流与带对带产生率成正比，因此在非局域隧道条件下，寻找隧道路径上的平均电场与应用栅极电压之间的显式关系是当前工作的主要挑战。为了得到通道区域电子能量分布的解析表达式，首先在矩形坐标系中求解二维泊松方程(具有拉普拉斯近似)。凯恩模型[J]。体育。化学。 Solids 12(181) 1959] for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET- like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

研究人员:Ramesha A, M.Sc. Engineering(2008)。

CMOS技术的不断缩小导致其性能的巨大改进。然而，目前的MOSFET开关的开关特性与理想的开关特性相差甚远。对于理想开关，次阈值摆动为零，这导致零离态电流。这种off-state电流是低待机功率应用(例如手机)最关键的参数，因为它决定了设备的电池寿命。由于载流子传输的漂移-扩散模式，目前MOSFET的亚阈值摆动的最小值在室温下被物理限制在60mV/decade。事实上，在超短通道MOSFET中，由于几种寄生效应(例如，穿孔，短通道效应等)，次阈值摆动进一步恶化。因此，对于未来低待机功率应用，需要使用不同类型载流子传输机制的备选MOSFET架构。本论文的目的是探索各种可用的选项，并提出一种CMOS兼容的技术，解决低待机功率应用中泄漏增加的问题。隧道场效应晶体管(TFET)具有完美的输出饱和特性、60mv /decade以下的亚阈值摆动和极高的ION/IOFF比，在此类应用中引起了广泛的关注。但由于IOFF极低，即使具有非常好的ION/IOFF比值，也无法满足ION的技术要求。 To overcome this problem of low ION, in this work, we have proposed a new Tunnel FET architecture with SiGe layer at the source end. The improvement in ION is achieved by modulating the bandgap at the tunneling junction by varying the Ge mole fraction in the SiGe layer. By the use of 2D device simulation, we demonstrate that the proposed device is scalable upto channel lengths as small as 30 nm. Also, the device becomes nearly free from DIBL as the germanium mole fraction is increased. A CMOS compatible process flow to fabricate the proposed device is discussed. The compatibility of the process flow with the standard CMOS process makes the proposed device highly attractive for future low stand-by power applications.

研究员:Nayan Bhogilal Patel, M.Sc. Engineering(2007)。

随着传统的硅金属氧化物半导体场效应晶体管(MOSFET)接近其缩放极限，许多新的器件结构正在被广泛探索。其中，硅纳米线场效应晶体管(Si- NWFET)受到了半导体业界和学术界的广泛关注。目前，一维硅纳米线因其优异的传输性能、紧凑的尺寸和与硅技术的兼容性而受到广泛关注。在纳米尺度下，利用基于量子力学方法的模拟技术来了解Si-NWFET的工作极限和性能极限已变得极其重要和必要。其中一种方法是非平衡格林函数(NEGF)形式主义。NEGF方法提供了量子输运和散射效应的严格描述。本工作研究了纳米级结构中最有前途的硅纳米场效应晶体管(Si-NWFET)的静电学和载流子动力学。通过对几个关键器件参数的缩放，观察了Si-NWFET在纳米尺度下性能的变化。使用量子力学模拟器(由nanohub.org提供)模拟和研究了si - nwfet中静电和载流子输运的量子力学效应。比较了专业器件模拟器(Sentaurus device)对多栅超薄体器件(Double gate-MOSFET和Si-NWFET)的半经典输运分析和量子力学模拟器的模拟结果，观察了纳米尺度下量子力学模拟的本质。 The Si-NWFET with rectangular and circular channel were simulated to compare the device characteristics. Finally, the performance of Si-NWFET is compared with Double gate-MOSFET.

研究员:Shubhakar，医学博士微(2007)。

单电子器件作为一种新兴的纳米技术，由于其超低功耗、新功能、纳米特征尺寸和CMOS兼容制造工艺而受到广泛关注。探索使用任何新技术构建逻辑门的可行性是当务之急。本文建立了SET逻辑的噪声裕度(NM)模型，该模型是器件电容和背景电荷(ζ)的函数。然后使用噪声裕度作为度量来评估SET逻辑对ζ、温度、SET参数(CT和CG)的变化以及点的能量量化的鲁棒性。结果表明，选择ζ = CT=CG = 1/3时，使NM最大化。最大可容忍ζ的估计，可以得到，并表明等于±0:03e。通过仿真研究了能量量化的影响，发现能量量化会降低SET逻辑的性能。最后，通过详细模拟研究了器件参数(CT和CG)不匹配对NM的影响，结果表明α Є[0.3, 0.4]具有最大的鲁棒性。还观察到失配对静态功率有巨大的影响。

研究者:Chaitanya Sathe, M.E. Micro(2007)。

在过去的十年里，电子领域在设备小型化、总功耗降低、系统便携性等方面发生了显著的发展。然而，对于现有的硅基技术，摩尔比例定律正在迅速接近其物理极限。随着器件尺寸的不断减小，漏极诱导势垒降低(DIBL)和VT滚转等短通道效应越来越突出。在探索石墨烯之后，研究者们对单层过渡金属二卤属化合物(TMDs)、hBN等二维层状材料产生了浓厚的兴趣。其中，tmd似乎是解决MOSFET缩放问题的好方法。他们提供良好的静电控制比他们的散装同行。此外，它们是共价键固体，其中相邻的堆叠层由弱范德华力保持。因此，它们可以很容易地剥离成单层，也没有悬空键。在各种tmd中，MoS2 (Molybednum Disulfide)似乎是理想的研究对象，因为它的直接带隙为1.8 eV，高开关电流比和相当好的载流子迁移率。然而，在MoS2晶体管的源/漏端实现低电阻接触是一个非常大的挑战。 This attributes to the low on-current in MoS2. Experimental techniques where local metallic phase is deposited on usual semiconducting MoS2 have attracted lot of attention. In conjunction with the experiments, density functional theory (DFT) based atomistic modeling of metal-2D material interface is important to get insights on the charge transfer through these systems. Therefore in this work, we have used DFT to compare the Schottky barrier height (SBH) of two polytypes of phase engineered MoS2 by calculating their elecronic structures. We also propose a novel asymmetric Au-MoS2-Au atomistic model to assess the carrier transport, estimate the contact resistance values of hetero interface using Non Equilibrium Green’s Function(NEGF) approach. We have shown that the contact resistance of Au-1T0-Au has decreased by three-fold compared to Au-2H-Au device.

研究人员:Richa Chakravarty, ME Micro(2016)。

多栅极(双栅极、三栅极或四栅极)MOSFET是取代传统块状MOSFET的必要器件，以便在未来CMOS缩放过程中不受阻碍。在双栅极器件中，独立双栅极(IDG) MOSFET由于两个栅极终端的独立控制，具有动态调节阈值电压和跨导的能力，从而提供了最大的设计灵活性。因此，开发基于表面势的紧凑模型来准确地描述IDG MOSFET的行为在最近受到了相当大的关注。这项工作旨在解决这一领域的一些潜在问题。基于表面电位的紧凑模型需要从泊松方程中快速准确地求解输入电压方程(称为P-IVEs或Primary IVEs)，以确定源极和漏极端的表面电位值，从而计算晶体管的其他物理参数。对于IDG MOSFET，隐式P-IVEs的鲁棒数值解需要使用根括号方法(rbm)，而不是常用的牛顿-拉弗森(NR)技术，因为P-IVEs中存在不可移动的不连续和奇异性。在这项工作中，对文献中可用的不同RBM进行了详尽的研究，并提出了一种单一的、无导数的RBM (LZ4)，它比先前提出的混合NR-Ridders算法具有更快的收敛速度，以求解IDG MOSFET的三角和双曲P-IVEs。通过对三角函数P-IVE的解空间进行一些调整，进一步减少了计算时间。通过Verilog-A接口和多种电路块的仿真，在商业电路模拟器中实现三角P-IVE后，计算效率提高了约60%，双曲P-IVE提高了约15%。终端费用的精确建模是紧凑模型的重要组成部分。 To overcome the limitations of the traditional charge linearization techniques for IDG MOSFET, a piecewise linearization technique for calculating the terminal charges is necessary. This requires formulating an additional set of IVEs, referred to as the S-IVEs or Secondary IVEs. The S-IVEs help to determine the surface potential at some pre- determined points along the channel. The nature of the Secondary IVEs is investigated here and an efficient solution methodology is proposed. The proposed solution is also implemented in a circuit simulator to compare the solution time with that for the P-IVEs. Although sufficiently accurate in predicting the device behavior in strong inversion, compact models for the IDG MOSFET based on the unipolar Poisson equation solution have a few limitations. These include the inability to accurately model the accumulation and near at band regions of operation. Varactor modeling of the IDG MOSFET also demands a complete solution of the bipolar Poisson equation. Here, we rigourously solve the Bipolar Poisson equation to derive an analytical model involving the Legendre’s incomplete elliptic integral of the rst kind and Jacobian elliptic functions. The proposed model is constructed along similar lines as that for the unipolar Poisson equation solution and it is seen that the device behavior is again governed by different sets of IVEs based on the bias condition. After investigating the solution space for the set of IVEs obtained, we employ the LZ4 RBM to solve the IVEs and obtain the potential profle for various bias conditions. The results thus obtained show good agreement with the numerical solution of the Poisson equation under all bias conditions.

研究人员:Abraham Aby, ME Micro(2012)。

准静态近似假定通道中任何位置的电荷密度随施加电压瞬时变化，即假定通道中的传输时间为零。更具体地说，如果QI = f(VD, VS, VG)(大写下标表示DC量)，QI = f(VD, VS, VG)，其中小写下标表示时变量。然而，由于通道传输时间不是零，基于准静态近似的分析引入了由于MOSFET的分布式特性而快速变化的终端电压的误差。在高频率下，传输时间lvd变得与终端交流电压的时间周期相当，因此在电压和通道电荷对电压的响应之间存在有限的时间滞后。将晶体管的分布特性考虑在内的模型被称为非准静态(NQS)模型。NQS模型的推导不是一项简单的任务，因为它需要同时求解传输方程和连续性方程。这项工作的目的是预测对称双栅极(SDG)和栅极全能(GAA)MOSFET在高频小信号变化和大信号快速瞬变下的行为。在小信号分析的情况下，时间变化可以用j!N，因此，问题简化为解常微分方程。高频分析大多是根据导纳(y)参数进行的，因此小信号分析的目标是观察器件y参数随频率的变化。 For large signal analysis, we have to solve a non linear parabolic partial differential equation. Here the main objective is to derive equations that can accurately predict the terminal currents when an input voltage of rise time sufficiently less than the transit time is applied. The large signal analysis is extremely rigorous and no complete analytical solution exists till date.

研究人员:Sudipta Sarkar, M.E. Micro(2010)。

由于FinFET的自对准工艺步骤和与传统的平面CMOS(互补金属氧化物半导体)技术的兼容性，它已成为在硅晶圆上实现多栅mosfet(金属氧化物半导体场效应晶体管)的最有前途的器件架构。一般的FinFET结构本质上是三栅(TG) MOSFET，可以通过适当缩放氧化层厚度转换为双栅或四栅MOSFET。虽然已经为对称双栅mosfet和非对称/独立双栅mosfet提出了几个分析模型，但尚未报道三栅晶体管的物理模型。这是由于解决二维泊松方程的复杂性，它的右手边有指数非线性。本文建立了TG FinFET反转电荷的解析模型，为建立紧凑模型奠定了基础。从控制二维泊松方程中，严格地表明TG FinFET中的总反转电荷可以分为三个分量:来自组成对称双栅(SDG)的电荷，来自组成独立双栅(IDG)的电荷和来自耦合分量的电荷。结果表明，由SDG和IDG分量产生的反转电荷的解析表达式可以从现有模型中得到，但很难得到耦合项的简化解析表达式。基于一些实际的近似，我们提出了一些建模耦合项的技术。使用这些技术获得的模型在广泛的设备参数范围内的所有操作制度下进行了数值模拟验证。在这一发展中，我们忽略了角效应，因为它是微不足道的非掺体装置。 While deriving the inversion charge model for FinFET, it is observed that previous techniques [Lu and Taur, IEEE Trans. Elec. Dev., Vol. 53,No. 5, 2006, Conde et al., IEEE Trans. Elec. Dev., Vol. 54, No. 1, 2007 and Liu et al., IEEE Trans. Elec. Dev., Vol. 55, No.3, 2008] used for solving the one-dimensional Poisson’s equation rigorously for long channel asymmetric and independent double gate transistor result in potential model that involves multiple inter-coupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This work also reports a different rigorous technique for solving the same Poisson equation by which one can obtain the potential profile of a generalized independent double gate transistor that involves a single implicit equation. Proposed model appears to be much more computationaly efficient for circuit simulation than the previous models.

研究员:Avinash Saho, M.Sc. Engineering(2009)。

基于硅纳米线的多栅金属氧化物场效应晶体管(MG-MOSFET)在45nm后技术节点中取代了传统的块状晶体管。在这种晶体管中，短通道效应(SCE)由器件几何形状控制，因此使用未掺杂(或轻掺杂)超薄体硅纳米线来维持通道。未掺杂体的使用也解决了体mosfet中的几个问题，例如随机掺杂波动、迁移率退化和与中间隙金属栅极的兼容性。这种器件的静电完整性随着本体厚度的减小而增大。由于在超薄体器件中电子能量的量子化是不可忽视的，因此在其阈值电压模型中考虑量子效应是极其重要的。目前报道的大多数模型都适用于长通道双栅极器件。只有Muntenu等人[非结晶固体杂志vol 351 pp 1911-1918 2005]报道了短通道对称双栅MOSFET的阈值电压模型，但它涉及非物理拟合参数。另一方面，除了数值模拟结果外，其他类型mg - mosfet(如三栅极、四栅极、圆柱体)的紧凑建模工作尚未报道。在这项工作中，我们报道了基于物理的闭形式量子阈值电压模型的短通道对称双栅极，四栅极和圆柱体栅极全能mosfet。在这些器件中，量子效应主要是由于电子能量的结构限制。 Proposed models are based on the analytical solution of two or three-dimensional Poisson equation and one or two-dimensional Schroedinger equation depending on the device geometries. Judicial approximations have been taken to simplify the models in order to make them closed form and efficient for large scale circuit simulation. Effort has also been put to model the quantum threshold voltage of tri gate MOSFET. However it is found that the energy quantization in tri gate devices are mainly due to electronic confinement and hence it is very difficult to develop closed form analytical equations for the threshold voltage. Thus in this work the modeling of tri gate devices have been limited to long channel cases. All the models are validated againt the professional numerical simulator.

研究员:P. Rakesh Kumar, M.Sc. Engineering(2009)。

在即将到来的sub-45nm技术节点中，未掺杂体多栅(MG)金属氧化物半导体场效应晶体管(MOSFET)正成为单栅体MOSFET的替代品。因此，为了将其用于纳米级集成电路的设计和仿真，开发紧凑型MG晶体管模型是非常必要的。然而，传统体晶体管的静电性能与非掺杂体器件之间有明显的区别。在块体晶体管中，衬底被充分掺杂，反转电荷位于靠近表面的位置，因此表面电位完全控制器件的静电完整性。而在非掺杂体器件中，栅极电场穿透体中心，反转电荷遍及体内。与体晶体管相比，在弱反转状态下，未掺杂体器件的体中心电位高于表面电位，电流通过器件中心而不是表面，这取决于器件几何形状。一些关键参数(如次阈值斜率)有时更依赖于身体中心的潜力，而不是表面。因此，为了准确计算无掺杂体多门晶体管的反转电荷、阈值电压等相关参数，还需要对体心电位和表面电位进行正确建模。虽然已经提出了几种MG晶体管的潜在模型来捕捉亚阈值状态下的短通道行为，但大多数模型都是基于将二维泊松方程转换为拉普拉斯方程的关键近似。这种近似只在表面有效，但在中心和适度反演情况下失效。 As a result all the previous models fail to capture the potential of body center correctly and remain valid only in weak-inversion regime. In this work we have developed semiclassical compact models for potential distribution for double gate (DG) and cylindrical Gate-All-Around (GAA) transistors. The models are based on the analytical solution of 2D Poisson’s equation in the channel region and valid for both: a) weak and strong inversion regimes, b) long channel and short channel transistors, and, c) body surface and center. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body thicknesses pass through a single common point (termed as crossover point). Using the concept of “crossover point” the effect of body thickness on the threshold voltage of undoped body multi-gate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. Some other parameters e.g. inversion charge, threshold voltage roll-off etc are also studied to demonstrate the impact of body center potential on the electrostatics of multi gate transistor. All the models are validated against professional numerical device simulator.

研究人员:Biswajit Ray, M.Sc. engineering(2008)。

互连构成了现代芯片设计中电路延迟的主要来源。随着技术规模的不断扩大，芯片互连也在缩小。现代VLSI技术中关键尺寸的变化导致了互连性能的变化，在时间验证中必须充分考虑到这一点。然而，处理大量的模间/模内变化并评估它们对电路性能的影响会极大地复杂化时序分析。在本文中，提出了一种实用的互连延迟变分分析技术，以方便有效地评估导线性能的变异性。通过将随机系数的电报方程转化为随机微分方程，建立了互连过程变异性的模型。我们测量了这种转换如何准确地将进程变化映射到输出延迟的可变性。随后，我们提出了一种新颖而有效的算法，用于在过程变化的情况下对互连网络进行建模。我们开发了一种考虑高斯金属工艺变化影响的互连延迟分析方法。将分布式RC线路的电阻和电容表示为独立的高斯随机变量，然后用它们来计算互连网络中所有节点的延迟概率分布函数的标准差。 We validate the accuracy of our approach against SPICE based Monte Carlo simulations while having greatly lowered the computational cost.

研究人员:Sivakumar Bondada, M.E. Micro(2008)。

隧道场效应晶体管(TFET)具有低于60mv /decade的亚阈值斜率和极高的离子/IOFF比，在电池寿命非常重要的低待机功率(LSTP)应用中引起了足够的关注。到目前为止，这方面的研究还局限于数值模拟和实验分析。然而，为了在纳米级集成电路设计和仿真中应用，开发紧凑的TFET模型是非常必要的。在这项工作中，我们首次建立了n通道双栅TFET (nDGTFET)的解析次阈值斜率模型。与传统的fet不同，TFET中的电流主要由源/通道接口的带对带隧道机制控制。由于总漏极电流与带对带产生率成正比，因此在非局域隧道条件下，寻找隧道路径上的平均电场与应用栅极电压之间的显式关系是当前工作的主要挑战。为了得到通道区域电子能量分布的解析表达式，首先在矩形坐标系中求解二维泊松方程(具有拉普拉斯近似)。凯恩模型[J]。体育。化学。 Solids 12(181) 1959] for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET- like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.

研究人员:Ramesha A, M.Sc. Engineering(2008)。

CMOS技术的不断缩小导致其性能的巨大改进。然而，目前的MOSFET开关的开关特性与理想的开关特性相差甚远。对于理想开关，次阈值摆动为零，这导致零离态电流。这种off-state电流是低待机功率应用(例如手机)最关键的参数，因为它决定了设备的电池寿命。由于载流子传输的漂移-扩散模式，目前MOSFET的亚阈值摆动的最小值在室温下被物理限制在60mV/decade。事实上，在超短通道MOSFET中，由于几种寄生效应(例如，穿孔，短通道效应等)，次阈值摆动进一步恶化。因此，对于未来低待机功率应用，需要使用不同类型载流子传输机制的备选MOSFET架构。本论文的目的是探索各种可用的选项，并提出一种CMOS兼容的技术，解决低待机功率应用中泄漏增加的问题。隧道场效应晶体管(TFET)具有完美的输出饱和特性、60mv /decade以下的亚阈值摆动和极高的ION/IOFF比，在此类应用中引起了广泛的关注。但由于IOFF极低，即使具有非常好的ION/IOFF比值，也无法满足ION的技术要求。 To overcome this problem of low ION, in this work, we have proposed a new Tunnel FET architecture with SiGe layer at the source end. The improvement in ION is achieved by modulating the bandgap at the tunneling junction by varying the Ge mole fraction in the SiGe layer. By the use of 2D device simulation, we demonstrate that the proposed device is scalable upto channel lengths as small as 30 nm. Also, the device becomes nearly free from DIBL as the germanium mole fraction is increased. A CMOS compatible process flow to fabricate the proposed device is discussed. The compatibility of the process flow with the standard CMOS process makes the proposed device highly attractive for future low stand-by power applications.

研究员:Nayan Bhogilal Patel, M.Sc. Engineering(2007)。

随着传统的硅金属氧化物半导体场效应晶体管(MOSFET)接近其缩放极限，许多新的器件结构正在被广泛探索。其中，硅纳米线场效应晶体管(Si- NWFET)受到了半导体业界和学术界的广泛关注。目前，一维硅纳米线因其优异的传输性能、紧凑的尺寸和与硅技术的兼容性而受到广泛关注。在纳米尺度下，利用基于量子力学方法的模拟技术来了解Si-NWFET的工作极限和性能极限已变得极其重要和必要。其中一种方法是非平衡格林函数(NEGF)形式主义。NEGF方法提供了量子输运和散射效应的严格描述。本工作研究了纳米级结构中最有前途的硅纳米场效应晶体管(Si-NWFET)的静电学和载流子动力学。通过对几个关键器件参数的缩放，观察了Si-NWFET在纳米尺度下性能的变化。使用量子力学模拟器(由nanohub.org提供)模拟和研究了si - nwfet中静电和载流子输运的量子力学效应。比较了专业器件模拟器(Sentaurus device)对多栅超薄体器件(Double gate-MOSFET和Si-NWFET)的半经典输运分析和量子力学模拟器的模拟结果，观察了纳米尺度下量子力学模拟的本质。 The Si-NWFET with rectangular and circular channel were simulated to compare the device characteristics. Finally, the performance of Si-NWFET is compared with Double gate-MOSFET.

研究员:Shubhakar，医学博士微(2007)。

单电子器件作为一种新兴的纳米技术，由于其超低功耗、新功能、纳米特征尺寸和CMOS兼容制造工艺而受到广泛关注。探索使用任何新技术构建逻辑门的可行性是当务之急。本文建立了SET逻辑的噪声裕度(NM)模型，该模型是器件电容和背景电荷(ζ)的函数。然后使用噪声裕度作为度量来评估SET逻辑对ζ、温度、SET参数(CT和CG)的变化以及点的能量量化的鲁棒性。结果表明，选择ζ = CT=CG = 1/3时，使NM最大化。最大可容忍ζ的估计，可以得到，并表明等于±0:03e。通过仿真研究了能量量化的影响，发现能量量化会降低SET逻辑的性能。最后，通过详细模拟研究了器件参数(CT和CG)不匹配对NM的影响，结果表明α Є[0.3, 0.4]具有最大的鲁棒性。还观察到失配对静态功率有巨大的影响。

研究者:Chaitanya Sathe, M.E. Micro(2007)。