研究员:Madhuchhanda Brahma (2019)

随着时间的推移，全球半导体研究界已经从近四十年的主导硅研究发展到寻找更新的晶体管材料，以追求更高的运行速度，同时降低功率、面积和成本。低有效质量材料，如III-V化合物是此类晶体管材料的最佳例子。为了在实际的晶体管设计和电子应用中使用这些材料，工程师必须有一套现成的数学模型，可以准确地预测器件的各种电子特性。因此，开发低有效质量通道材料晶体管的标准紧凑模型对于将这些神奇材料应用于现实生活至关重要。

紧凑建模是一种将电子设备中极其繁琐和复杂的物理转化为一组可预测的、便携式的、健壮的和计算效率高的分析方程的艺术，可以用于实时电路设计。现有的低有效质量通道材料的紧凑模型存在许多关键的局限性，例如只处理对称的氧化层厚度，过度使用非物理方法和经验拟合参数等。通过我们的工作-第一次提出并实现了一个完全物理的，健壮的，便携式的低有效质量通道普通双栅MOSFET紧凑模型。该模型结合了精确且计算效率高的表面势方程(SPE)和耦合薛定谔-泊松方程的解析解;基于量子漂移扩散(QDD)的电流传输和终端电荷模型，并包含DIBL效应。由于巨大的量子限制，每个能量子带的准费米能级彼此保持距离，因为载流子保持在各自子带的热平衡中。这种由强量子限制引起的准费米能级的偏析严重影响了半导体通道中的输运，从而将输运从硅mosfet中的正常漂移-扩散转变为低有效质量通道mosfet中的QDD。

模型开发从几个合理的逻辑假设开始，这些假设在随后的阶段中得到了尽可能好的补偿。在平坦带条件下，导出了信道中特定子带对应的波函数。它在模型开发过程中一直使用，在最后阶段通过引入解析推导的修正因子对模型进行补偿。各个子带能量也在基态下得到，在后期通过摄动技术解决它们的偏置依赖性。在模拟传输时，单个子带的通道电荷密度沿通道随子带能量线性变化，从而形成电流与通道电荷密度的平方定律模型。所提出的模型的独特性在于它精确地处理了多个问题，如氧化层厚度的不对称性、波函数穿透、偏置依赖的扩散率、量子漂移-扩散输运、多子带载流子占用和宽范围的材料有效质量、器件厚度以及输入电压，而无需使用单一的非物理多项式拟合或经验常数。同时保留了工业标准硅MOSFET模型的数学清晰度。提出的模型通过各种器件几何形状、氧化物不对称、材料特性的数值TCAD仿真验证，并通过verilog-A接口在专业电路模拟器中成功实现。通过这项工作，首次将基本的量子漂移-扩散输运引入到电路模拟中，此前仅局限于器件模拟，从而开辟了使用低有效质量材料设计电路的可能性。

研究员:Ananda Sankar Chakraborty (2019)

近年来，利用第一性原理的原子建模技术对纳米材料和结构的各种局部调制电子特性进行了深入研究。原子建模提供了预测晶体结构、可视化轨道分布和电子密度的好处，以及理解难以通过实验获得的材料特性。

单层MoS2由于其独特的电学、光学和力学性能，如更好的静电性能、增强的光致发光性能、更高的机械柔性等，已成为下一代纳米器件的合适选择。以单层二硫化钼为通道的癸量级数字开关的实现具有高开/关电流比、极好的栅极静电控制、低泄漏等显著优点。

然而，要在集成电路中成功实现原子薄晶体管，还需要解决一些关键问题，如形成低电阻的源/漏触点，实现更高的有效迁移率，确保大规模的可控增长等。最近的实验证明，在同一单层MoS2中，金属相和半导体相共存，因其在超低接触电阻MoS2晶体管中的应用而引起了广泛的关注。然而，金属-半导体相边界的电子结构，似乎决定了这种晶体管中的载流子注入，还没有很好地理解。

在这项工作中，我们首先建立了具有两个明显相边界β和γ的2H- 1T’异相结构的几何优化原子模型。然后应用密度泛函理论计算了优化后的基因组的电子结构。此外，我们采用非平衡格林函数形式来评估传输光谱和局部状态密度，以评估相位边界的肖特基势垒性质。

然而，源-通道和漏-通道结的对称性是金属氧化物半导体场效应晶体管(MOSFET)的独特特性，在使用先进技术实现10nm以下通道长度的器件时需要保持这一特性。利用实验结果驱动的原子建模技术，我们证明了这种对称性可能不会在原子薄相工程MoS2基MOSFET中被保留。当半导体相(通道)夹在两个金属相(源相和漏相)之间时，它起源于相边界(β和β*)上的两种不同的原子模式。

接下来，利用基于第一性原理的量子输运计算，我们证明了由于1T’MoS2中“Mo”原子的聚类，沿之字形方向的输运明显高于扶手椅方向的输运。此外，为了与各种金属触点(如“Au”，“Pd”等)实现良好的阻抗匹配，我们进一步建立了金属- 1t’MoS2边缘接触几何结构的原子模型，并计算其电阻值。

除了载流子传输，分析跨通道的热传输在设计下一代超薄晶体管时也是至关重要的。因此，在本论文工作中，我们研究了单层二硫化钼在准弹道状态下的电热输运特性。除了原始形态的完美单分子层，我们还考虑了在机械剥离的MoS2样品中实验观察到的各种线缺陷。此外，本文还对悬浮单层MoS2的声子热导率进行了全面研究。

本文的研究对于理解原子薄器件中的载流子传输以及设计下一代超薄晶体管具有重要意义。

研究人员:Dipankar Saha (2017)

摩尔定律无法缩小次癸纳计体系中的技术节点，也无法生产有效的高性能逻辑器件。因此，ITRS趋势有望概念化新型器件结构，如极薄绝缘体上硅(ETSOI)、多栅FET (mugfet)或finfet，并探索新的二维材料作为FET的合适通道材料。单层石墨烯剥离后，许多二维材料被用来取代块状硅作为通道材料，如TMD、黑磷等。虽然基于半导体原子薄层状材料的场效应晶体管可以提供优异的静电完整性，但实验器件中的ON电流与所需的相比较低。源/漏端金属-半导体界面的肖特基势垒高度(SBH)被认为是低ON电流值的可能原因之一。实验证明了许多技术，并探索了新的二维材料，旨在降低SBH和提高ON电流值。然而，导致SBH还原的界面化学并没有被有效地探索，因为在原子水平上实验访问这一现象是相当具有挑战性的。因此，本论文运用早期在石墨烯-金属接触研究中得到有效应用的密度泛函理论(DFT)，对各种二维材料-金属界面的理论视角进行了全面深入的研究。该研究完全按照系统的方法组织:创建优化的界面几何结构，估计平衡层间距离，分析界面上的势垒，探索电荷转移和界面偶极子，研究轨道杂化，最后评估SBH。交换相关函数，伪势和基集是为每个界面结构选择适当和非常谨慎的，以产生精确的电子结构。 Firstly we outline our methodology to study a 2D material-metal contact. The first application of our methodology is for an interface formed between the metal (gold, palladium and titanium) and puckered honeycomb monolayer of black phosphorous (i.e. phosphorene). Following it, we analyze a graphene inserted MoS2-metal interface (titanium, silver, ruthenium, gold and platinum), ranging from metal with low work function to high work function. Furthermore, we continue our study for p-type niobium doped MoS2 and its contact with gold. Apart from p type TMD, n-type chlorine doped WS2 and its contact with gold and palladium is also examined for this study. Doping graphene with BN is one among the possible choices to open band gap in pristine graphene. In the next part we study these materials and analyze various defects such as stone-wales and vacancy on the performance of boron-nitride embedded graphene nanoribbon transistor.

研究人员:Anuja Chanana (2016)

紧凑模型是基于物理的电路元件的精确数学描述，其计算效率足够高，可以合并到电路模拟器中，从而使结果对电路设计者有用。由于多栅极mosfet已经出现在32nm以下的技术节点上，作为大块mosfet的替代品，这些新型晶体管的高效紧凑模型是它们在集成电路中的成功应用所必需的。现有的普通双栅(CDG) mosfet的紧凑模型是基于具有对称栅氧化厚度的基本假设。在这项工作中，我们探索了在没有这种近似的情况下开发模型的可能性，同时将计算效率保持在同一水平。这种努力旨在推广紧凑模型，并捕捉氧化层厚度不对称效应，由于工艺的不确定性，这种效应可能在实际设备中普遍存在，从而显著影响设备性能。然而，由于静电的偏倚不对称性质，这个建模问题的解决是不平凡的。利用“基于单隐式方程的泊松解”和“表面势之间独特的准线性关系”，我们实验室之前的研究人员已经报道了这种非对称CDG MOSFET的“核心”模型。在这项工作中，我们努力将非准静态(NQS)效应、不同的小几何效应和噪声模型纳入这个“核心”，使模型适合于实际应用。结果表明，在NQS条件下，在所有小几何效应存在的情况下，表面势之间的准线性关系仍然保持不变。该设备的这一特性以及一些其他新技术被用于开发模型，同时保持对称设备报告的模型的数学复杂性在同一水平。 Proposed model is verified against TCAD simulation for various device geometries and successfully implemented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

研究人员:Neha Sharan (2014)

由于CMOS技术的大幅缩小，芯片内部的功率和电流密度正在增加。现有互连材料的极限电流传导容量(106 Acm-2)和热导率(201 Wm-1K-1 Al和400 Wm-1K-1 Cu)引起了不同的电热问题，如热点形成、电迁移等。因此，探索具有高导热性和高导流性的新材料成为未来集成电路技术的热点。在所有单质材料中，碳纳米材料(石墨烯和碳纳米管)在室温下具有极高的导热性能(600-7000 Wm-1K-1)和电流~ 108 - 109 Acm-2)，这使它们成为潜在的互连材料候选材料。与此同时，开发高效的能量收集技术对于未来的无线自主设备也变得越来越重要。在热点位置产生的多余热量可以用来通过合适的热电发电机驱动电子电路。石墨烯的塞贝克系数是所有基本半导体中最高的，因此对其热电性能的研究非常重要。本文研究了金属单壁碳纳米管(SWCNT)和单层石墨烯(SLG)的电热和热电性能，以探讨其在下一代集成电路热管理中的应用前景。基于三声子Umklapp、质量差和边界散射现象，考虑温度相关的晶格热导率(κ)，提出了金属SWCNTs中焦耳-加热方程的封闭解析解。其解决方案给出了SWCNT长度上的温度分布，因此可以预测热点的位置(由于芯片内部的自热而产生)。 This self-heating phenomenon is further extended to estimate the electromigration performance and mean-time-to-failure of metallic SWCNTs. It is shown that metallic SWCNTs are less prone to electromigration. To analyze the electro-thermal effects in a suspended SLG, a physics-based flexural phonon dominated thermal conductivity model is developed, which shows that κ follows a T1.5 and T-2 law at lower (less than 300) K and higher temperature respectively in the absence of isotopes (C13 atoms). However in the presence of isotopic impurity, the behavior of κ sharply deviates from T-2 at higher temperatures. The proposed model of κ is found to be in excellent match with the available experimental data over a wide range of temperatures and can be utilized for an efficient electro-thermal analysis of encased/supported graphene. By considering the interaction of electron with in-plane and flexural phonons in a doped SLG sheet, a physics-based electrical conductance (σ) model of SLG under self-heating effect is also discussed that particularly exhibits the variation of electrical resistance with temperature at different current levels and matches well with the available experimental data. To investigate the thermoelectric performance of a SLG sheet, analytical models for Seebeck effect coefficient (SB) and specific heat (Cph) are developed, which are found to be in good agreement with the experimental data. Using those analytical models, it is predicted that one can achieve a thermoelectric figure of merit (ZT) of ~ 0.62 at room temperature by adding isotopic impurities (C13 atoms) in a degenerate SLG. Such prediction shows the immense potential of graphene in waste-heat recovery applications. Those models for σ, κ, SB and Cph are further used to determine the time evolution of temperature distribution along suspended SLG sheet through a transient analysis of Joule-heating equation under the Thomson effect. The proposed methodology can be extended to analyze the graphene heat-spreader theory and interconnects and graphene based thermoelectrics.

研究人员:Rekha Verma (2013)

超越摩尔定律的技术扩展需要在10纳米以下的栅极长度扩展的尖端解决方案，以实现低功耗高速运行。最近，SOI技术受到了相当多的关注，但在未来的纳米电子技术中，sub- 10nm技术的可制造解决方案尚不清楚。因此，为了继续在sub- 10nm区域进行缩放，新的一维(1D)和二维(2D)“纳米材料”和工程有望跟上步伐。然而，要想在未来的硅纳米技术中发挥作用，载流子传输中的纳米材料特性必须克服重大挑战。因此，了解和调节它们的电子带结构和输运特性对于低功率纳米电子的应用非常重要。本文试图为这方面的一些问题提供解决方案。近年来，一维硅纳米线已成为下一代纳米电子器件的基石，因为它可以容纳多栅晶体管结构，具有优异的静电完整性。然而，由于在纳米尺度下的各种能带参数的实验研究极具挑战性，通常依赖于原子级的模拟，其结果与实验观测结果相当。其中两个参数是带隙和有效质量，它们对于理解当前的输运机制具有开拓性的重要性。虽然松弛硅纳米线的带隙存在大量的经验关系，但人们越来越需要开发基于物理的分析模型来标准化不同的能带参数，这尤其需要将其应用于TCAD软件中，用于预测新器件的不同电特性，以及其应变对应的器件，以在不改变器件结构的情况下显著提高器件特性。 The first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moorefs law devices also demands the SOI body thickness, Tsi–> The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide meterials (MX2) (M = Mo, W; X = S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials (except WTe2) in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of those MX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthreshold slope of 150 µA/µm and 4 mV/dec, respectively. However, only the MoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.

研究员:Ram Krishna Ghosh (2013)

独立双栅极(IDG)金属氧化物半导体场效应晶体管(MOSFET)由于具有动态调节阈值电压和跨导的能力，近年来受到了广泛的关注。由于静电的不对称性质，与对称双栅晶体管相比，开发这种器件的高效紧凑模型是一项艰巨的任务。本文试图针对这方面的一些问题提出解决方案。通过求解一维泊松方程(PE)对长通道电势进行建模是开发基于表面电势的此类晶体管核心紧凑模型的最基本步骤。以往严格求解长通道非对称独立双栅极晶体管一维泊松方程的方法，得到的势模型涉及多个相互耦合的隐式方程。由于这些方程需要自洽求解，这种潜在模型对于紧凑建模显然是低效的。这项工作报告了一种不同的解决同一泊松方程的严格技术，通过它可以获得涉及单个隐式方程的广义独立双栅晶体管的电位剖面。所提出的泊松解决方案在电路仿真计算效率上至少比以前的解决方案高5倍。开发高效的终端收费模型是迈向紧凑建模的另一个关键步骤。在这项工作中，我们展示了传统的电荷线性化技术在模拟IDG mosfet的终端电荷时的局限性。 We propose a new charge linearization technique in order to model the terminal charges and transcapacitances of the IDG MOSFETs. We report two different types of quasi-static large signal models for the long channel device. In the first type, the terminal charges are expressed as closed form functions of source and drain end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on quadratic spline collocation technique and requires the input voltage equation to be solved two more times apart from the source and drain end. Proposed model has been successfully implemented in professional circuit simulator. Voltage controlled oscillators (VCOs) based on metal oxide semiconductor (MOS) varactors have become an integral part of RF communication circuits. An independently controlled double gate based MOS capacitor can bring out new functionalities, which could be interesting for RF circuit applications. For the first time, this work, explores the characteristics of MOS capacitor controlled by independent double gates by numerical simulation and analytical modeling for its possible use in RF circuit design as a varactor. By numerical simulation it is shown how the quasi-static and non-quasi-static characteristics of the first gate capacitance could be tuned by the second gate biases. Analytical solution of complete (considering both electron and hole concentration) Poisson equation (PE) is proposed. A new set of input voltage equations (IVEs) for independent double gate MOSFET are proposed by solving the governing bipolar Poisson equation rigorously. The proposed IVEs, involve the Legendre’s incomplete elliptic integral of the first kind andJacobian elliptic functions and are valid from accumulation to inversion regimes. As Legendre’s incomplete elliptic integral of first kind and Jacobian elliptic functions are computationally expensive, hence I also propose a semi-empirical solution using previous analytical solution of the PE for IDG MOS capacitor considering only electron/hole. Proposed models, which are valid from accumulation to inversion, are shown to have excellent agreement with numerical simulation for practical bias conditions.

研究员:Pankaj Kumar Thakur (2013)

在过去的40年里，对摩尔定律晶体管缩放的不懈关注提供了不断增长的晶体管性能和密度。为了继续将技术扩展到22nm节点以上，很明显，传统的大块mosfet需要被新的器件架构所取代，最有希望的是多门mosfet mufet)。英特尔在2011年年中宣布在其下一代IvyBridge微处理器的22nm高容量逻辑工艺中使用批量三门finfet。预计很快其他半导体公司也将采用muget器件。与大体积MOSFET一样，精确且物理紧凑的模型对于基于mufet的电路设计至关重要。平面双栅MOSFET (DGFET)的紧凑建模工作始于90年代末，因为它是人们可以为mufet器件设想的最简单的结构。目前为DG mosfet提出的模型适用于共用栅极对称的DG (SDG) mosfet，其中两个栅极具有相同的氧化厚度。然而，对于实际的纳米级器件，由于工艺变化和不确定性，栅极氧化物厚度之间总是存在一定程度的不对称，这可能会显著影响器件性能。与此同时，独立控制DG (IDG) mosfet因其动态调节阈值电压和跨导的能力而受到广泛关注。由于静电的不对称性质，开发高效紧凑的非对称/独立DG MOSFET模型是一项艰巨的任务。 In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations 1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG (IDG) MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate (DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demon- strate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

研究人员:J. Srivatsava (2013)

尽管CMOS(互补金属氧化物半导体)技术的扩展预计还将持续10年，但需要新的技术解决方案来克服癸量计MOS晶体管的基本限制。单电子晶体管(SET)因其独特的库仑封锁振荡特性、超低功耗和纳米尺度的特征尺寸而备受关注。尽管潜力巨大，但由于一些固有的限制(例如，非常低的电流驱动)，SET很难与CMOS的大规模基础设施、经过验证的设计方法和经济可预测性进行正面竞争。然而，SET和MOS晶体管的特性是互补的。SET提倡低功耗和新功能(与库仑封锁振荡有关)，而CMOS具有高速驱动和电压增益等优势，可以弥补SET的内在缺点。因此，虽然单电子器件完全取代CMOS在不久的将来是不可能的，但将SET和CMOS结合起来可以带来纯CMOS技术无法反映的新功能。随着CMOS和SET的杂交越来越受欢迎，硅SET在与CMOS的可能集成方面似乎比金属SET更有前途。集合通常是在经典的正统理论的基础上研究的，其中岛上的能量态的量子化完全被忽略了。尽管这一假设极大地简化了所涉及的物理过程，但只有当SET是由金属岛构成时，这一假设才成立。由于半导体孤岛中能量态的量子化是不可忽视的，因此研究能量量子化对CMOS-SET混合集成电路的影响就显得尤为重要。 The main objective of this thesis is to understand energy quantization effects on SET by numerical simulations, develop simple analytical models that can capture the energy quantization effects, analyze the effects of energy quantization on SET logic inverter, and finally, develop a CAD framework for CMOS-SET co-simulation and to study the effect on energy quantization on hybrid circuits using that framework. In this work the widely accepted SIMON Monte Carlo (MC) simulator for single electron devices and circuits is used to study the effect of energy quantization. So far SIMON has been used to study SETs having metallic island. In this work, for the first time, we have shown how one can use SIMON to analyze SET island properties having discrete energy states. It is shown that energy quantization mainly changes the Coulomb Blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET logic inverter. A new model for the noise margin of SET inverter is proposed, which includes the energy quantization term. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “Quantization Threshold”) that an SET inverter logic circuit can withstand before its noise margin falls below a specified tolerance level. It is found that SET inverter designed with CT : CG = 0.366 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization. Then the effects of energy quantization are studied for Current biased SET (CBS), which is an integral part of almost all hybrid CMOS-SET circuits. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics though it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: Negative Differential Resistance (NDR) and Neurone Cell, which use CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. A novel CAD framework is then developed for CMOS-SET co-simulation, which uses MC simulator for SET devices along with conventional SPICE. Using this framework, the effects of energy quantization are studied for some hybrid circuits, namely, SETMOS, multiband voltage filter, and multiple valued logic circuits. It is found that energy quantization degrades the performance of hybrid circuit, which could be compensated by properly tuning the bias current of SET devices. Though this study is primarily done by exhaustive MC simulation, effort has also been put to develop first order compact model for SET that includes energy quantization effects. Finally it is demonstrated that one can predict the SET behavior under energy quantization with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

研究者:Surya Shankar Dan (2009)

研究员:Madhuchhanda Brahma (2019)

随着时间的推移，全球半导体研究界已经从近四十年的主导硅研究发展到寻找更新的晶体管材料，以追求更高的运行速度，同时降低功率、面积和成本。低有效质量材料，如III-V化合物是此类晶体管材料的最佳例子。为了在实际的晶体管设计和电子应用中使用这些材料，工程师必须有一套现成的数学模型，可以准确地预测器件的各种电子特性。因此，开发低有效质量通道材料晶体管的标准紧凑模型对于将这些神奇材料应用于现实生活至关重要。

紧凑建模是一种将电子设备中极其繁琐和复杂的物理转化为一组可预测的、便携式的、健壮的和计算效率高的分析方程的艺术，可以用于实时电路设计。现有的低有效质量通道材料的紧凑模型存在许多关键的局限性，例如只处理对称的氧化层厚度，过度使用非物理方法和经验拟合参数等。通过我们的工作-第一次提出并实现了一个完全物理的，健壮的，便携式的低有效质量通道普通双栅MOSFET紧凑模型。该模型结合了精确且计算效率高的表面势方程(SPE)和耦合薛定谔-泊松方程的解析解;基于量子漂移扩散(QDD)的电流传输和终端电荷模型，并包含DIBL效应。由于e
在标准量子限制下，每个能量子带的准费米能级彼此保持距离，因为载流子在各自的子带中保持热平衡。这种由强量子限制引起的准费米能级的偏析严重影响了半导体通道中的输运，从而将输运从硅mosfet中的正常漂移-扩散转变为低有效质量通道mosfet中的QDD。

模型开发从几个合理的逻辑假设开始，这些假设在随后的阶段中得到了尽可能好的补偿。在平坦带条件下，导出了信道中特定子带对应的波函数。它在模型开发过程中一直使用，在最后阶段通过引入解析推导的修正因子对模型进行补偿。各个子带能量也在基态下得到，在后期通过摄动技术解决它们的偏置依赖性。在模拟传输时，单个子带的通道电荷密度沿通道随子带能量线性变化，从而形成电流与通道电荷密度的平方定律模型。所提出的模型的独特性在于它精确地处理了多个问题，如氧化层厚度的不对称性，波函数穿透，偏压依赖扩散率，量子
Drift-D
夹杂输运，多子带载流子占用和宽范围的材料有效质量，器件厚度随输入电压-而不使用单一的非物理多项式拟合或经验常数，同时保留工业标准硅MOSFET模型的数学清晰度。提出的模型通过各种器件几何形状、氧化物不对称、材料特性的数值TCAD仿真验证，并通过verilog-A接口在专业电路模拟器中成功实现。通过这项工作，首次将基本的量子漂移-扩散输运引入到电路模拟中，此前仅局限于器件模拟，从而开辟了使用低有效质量材料设计电路的可能性。

研究员:Ananda Sankar Chakraborty (2019)

近年来，利用第一性原理的原子建模技术对纳米材料和结构的各种局部调制电子特性进行了深入研究。原子建模提供了预测晶体结构、可视化轨道分布和电子密度的好处，以及理解难以通过实验获得的材料特性。

单层MoS2由于其独特的电学、光学和力学性能，如更好的静电性能、增强的光致发光性能、更高的机械柔性等，已成为下一代纳米器件的合适选择。以单层二硫化钼为通道的癸量级数字开关的实现具有高开/关电流比、极好的栅极静电控制、低泄漏等显著优点。

然而，要在集成电路中成功实现原子薄晶体管，还需要解决一些关键问题，如形成低电阻的源/漏触点，实现更高的有效迁移率，确保大规模的可控增长等。最近的实验证明，在同一单层MoS2中，金属相和半导体相共存，因其在超低接触电阻MoS2晶体管中的应用而引起了广泛的关注。然而，金属-半导体相边界的电子结构，似乎决定了这种晶体管中的载流子注入，还没有很好地理解。

在这项工作中，我们首先建立了具有两个明显相边界β和γ的2H- 1T’异相结构的几何优化原子模型。然后应用密度泛函理论计算了优化后的基因组的电子结构。此外，我们采用非平衡格林函数形式来评估传输光谱和局部状态密度，以评估相位边界的肖特基势垒性质。

然而，源-通道和漏-通道结的对称性是金属氧化物半导体场效应晶体管(MOSFET)的独特特性，在使用先进技术实现10nm以下通道长度的器件时需要保持这一特性。利用实验结果驱动的原子建模技术，我们证明了这种对称性可能不会在原子薄相工程MoS2基MOSFET中被保留。当半导体相(通道)夹在两个金属相(源相和漏相)之间时，它起源于相边界(β和β*)上的两种不同的原子模式。

接下来，利用基于第一性原理的量子输运计算，我们证明了由于1T’MoS2中“Mo”原子的聚类，沿之字形方向的输运明显高于扶手椅方向的输运。此外，为了与各种金属触点(如“Au”，“Pd”等)实现良好的阻抗匹配，我们进一步建立了金属- 1t’MoS2边缘接触几何结构的原子模型，并计算其电阻值。

除了载流子传输，分析跨通道的热传输在设计下一代超薄晶体管时也是至关重要的。因此，在本论文工作中，我们研究了单层二硫化钼在准弹道状态下的电热输运特性。除了原始形态的完美单分子层，我们还考虑了在机械剥离的MoS2样品中实验观察到的各种线缺陷。此外，本文还对悬浮单层MoS2的声子热导率进行了全面研究。

本文的研究对于理解原子薄器件中的载流子传输以及设计下一代超薄晶体管具有重要意义。

研究人员:Dipankar Saha (2017)

摩尔定律无法缩小次癸纳计体系中的技术节点，也无法生产有效的高性能逻辑器件。因此，ITRS趋势有望概念化新型器件结构，如极薄绝缘体上硅(ETSOI)、多栅FET (mugfet)或finfet，并探索新的二维材料作为FET的合适通道材料。单层石墨烯剥离后，许多二维材料被用来取代块状硅作为通道材料，如TMD、黑磷等。虽然基于半导体原子薄层状材料的场效应晶体管可以提供优异的静电完整性，但实验器件中的ON电流与所需的相比较低。源/漏端金属-半导体界面的肖特基势垒高度(SBH)被认为是低ON电流值的可能原因之一。实验证明了许多技术，并探索了新的二维材料，旨在降低SBH和提高ON电流值。然而，导致SBH还原的界面化学并没有被有效地探索，因为在原子水平上实验访问这一现象是相当具有挑战性的。因此，本论文运用早期在石墨烯-金属接触研究中得到有效应用的密度泛函理论(DFT)，对各种二维材料-金属界面的理论视角进行了全面深入的研究。该研究完全按照系统的方法组织:创建优化的界面几何结构，估计平衡层间距离，分析界面上的势垒，探索电荷转移和界面偶极子，研究轨道杂化，最后评估SBH。交换相关函数，伪势和基集是为每个界面结构选择适当和非常谨慎的，以产生精确的电子结构。 Firstly we outline our methodology to study a 2D material-metal contact. The first application of our methodology is for an interface formed between the metal (gold, palladium and titanium) and puckered honeycomb monolayer of black phosphorous (i.e. phosphorene). Following it, we analyze a graphene inserted MoS2-metal interface (titanium, silver, ruthenium, gold and platinum), ranging from metal with low work function to high work function. Furthermore, we continue our study for p-type niobium doped MoS2 and its contact with gold. Apart from p type TMD, n-type chlorine doped WS2 and its contact with gold and palladium is also examined for this study. Doping graphene with BN is one among the possible choices to open band gap in pristine graphene. In the next part we study these materials and analyze various defects such as stone-wales and vacancy on the performance of boron-nitride embedded graphene nanoribbon transistor.

研究人员:Anuja Chanana (2016)

紧凑模型是基于物理的电路元件的精确数学描述，其计算效率足够高，可以合并到电路模拟器中，从而使结果对电路设计者有用。由于多栅极mosfet已经出现在32nm以下的技术节点上，作为大块mosfet的替代品，这些新型晶体管的高效紧凑模型是它们在集成电路中的成功应用所必需的。现有的普通双栅(CDG) mosfet的紧凑模型是基于具有对称栅氧化厚度的基本假设。在这项工作中，我们探索了在没有这种近似的情况下开发模型的可能性，同时将计算效率保持在同一水平。这种努力旨在推广紧凑模型，并捕捉氧化层厚度不对称效应，由于工艺的不确定性，这种效应可能在实际设备中普遍存在，从而显著影响设备性能。然而，由于静电的偏倚不对称性质，这个建模问题的解决是不平凡的。利用“基于单隐式方程的泊松解”和“表面势之间独特的准线性关系”，我们实验室之前的研究人员已经报道了这种非对称CDG MOSFET的“核心”模型。在这项工作中，我们努力将非准静态(NQS)效应、不同的小几何效应和噪声模型纳入这个“核心”，使模型适合于实际应用。结果表明，在NQS条件下，在所有小几何效应存在的情况下，表面势之间的准线性关系仍然保持不变。该设备的这一特性以及一些其他新技术被用于开发模型，同时保持对称设备报告的模型的数学复杂性在同一水平。 Proposed model is verified against TCAD simulation for various device geometries and successfully implemented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

研究人员:Neha Sharan (2014)

由于CMOS技术的大幅缩小，芯片内部的功率和电流密度正在增加。现有互连材料的极限电流传导容量(106 Acm-2)和热导率(201 Wm-1K-1 Al和400 Wm-1K-1 Cu)引起了不同的电热问题，如热点形成、电迁移等。因此，探索具有高导热性和高导流性的新材料成为未来集成电路技术的热点。在所有单质材料中，碳纳米材料(石墨烯和碳纳米管)在室温下具有极高的导热性能(600-7000 Wm-1K-1)和电流~ 108 - 109 Acm-2)，这使它们成为潜在的互连材料候选材料。与此同时，开发高效的能量收集技术对于未来的无线自主设备也变得越来越重要。在热点位置产生的多余热量可以用来通过合适的热电发电机驱动电子电路。石墨烯的塞贝克系数是所有基本半导体中最高的，因此对其热电性能的研究非常重要。本文研究了金属单壁碳纳米管(SWCNT)和单层石墨烯(SLG)的电热和热电性能，以探讨其在下一代集成电路热管理中的应用前景。基于三声子Umklapp、质量差和边界散射现象，考虑温度相关的晶格热导率(κ)，提出了金属SWCNTs中焦耳-加热方程的封闭解析解。其解决方案给出了SWCNT长度上的温度分布，因此可以预测热点的位置(由于芯片内部的自热而产生)。 This self-heating phenomenon is further extended to estimate the electromigration performance and mean-time-to-failure of metallic SWCNTs. It is shown that metallic SWCNTs are less prone to electromigration. To analyze the electro-thermal effects in a suspended SLG, a physics-based flexural phonon dominated thermal conductivity model is developed, which shows that κ follows a T1.5 and T-2 law at lower (less than 300) K and higher temperature respectively in the absence of isotopes (C13 atoms). However in the presence of isotopic impurity, the behavior of κ sharply deviates from T-2 at higher temperatures. The proposed model of κ is found to be in excellent match with the available experimental data over a wide range of temperatures and can be utilized for an efficient electro-thermal analysis of encased/supported graphene. By considering the interaction of electron with in-plane and flexural phonons in a doped SLG sheet, a physics-based electrical conductance (σ) model of SLG under self-heating effect is also discussed that particularly exhibits the variation of electrical resistance with temperature at different current levels and matches well with the available experimental data. To investigate the thermoelectric performance of a SLG sheet, analytical models for Seebeck effect coefficient (SB) and specific heat (Cph) are developed, which are found to be in good agreement with the experimental data. Using those analytical models, it is predicted that one can achieve a thermoelectric figure of merit (ZT) of ~ 0.62 at room temperature by adding isotopic impurities (C13 atoms) in a degenerate SLG. Such prediction shows the immense potential of graphene in waste-heat recovery applications. Those models for σ, κ, SB and Cph are further used to determine the time evolution of temperature distribution along suspended SLG sheet through a transient analysis of Joule-heating equation under the Thomson effect. The proposed methodology can be extended to analyze the graphene heat-spreader theory and interconnects and graphene based thermoelectrics.

研究人员:Rekha Verma (2013)

超越摩尔定律的技术扩展需要在10纳米以下的栅极长度扩展的尖端解决方案，以实现低功耗高速运行。最近，SOI技术受到了相当多的关注，但在未来的纳米电子技术中，sub- 10nm技术的可制造解决方案尚不清楚。因此，为了继续在sub- 10nm区域进行缩放，新的一维(1D)和二维(2D)“纳米材料”和工程有望跟上步伐。然而，要想在未来的硅纳米技术中发挥作用，载流子传输中的纳米材料特性必须克服重大挑战。因此，了解和调节它们的电子带结构和输运特性对于低功率纳米电子的应用非常重要。本文试图为这方面的一些问题提供解决方案。近年来，一维硅纳米线已成为下一代纳米电子器件的基石，因为它可以容纳多栅晶体管结构，具有优异的静电完整性。然而，由于在纳米尺度下的各种能带参数的实验研究极具挑战性，通常依赖于原子级的模拟，其结果与实验观测结果相当。其中两个参数是带隙和有效质量，它们对于理解当前的输运机制具有开拓性的重要性。虽然松弛硅纳米线的带隙存在大量的经验关系，但人们越来越需要开发基于物理的分析模型来标准化不同的能带参数，这尤其需要将其应用于TCAD软件中，用于预测新器件的不同电特性，以及其应变对应的器件，以在不改变器件结构的情况下显著提高器件特性。 The first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moorefs law devices also demands the SOI body thickness, Tsi–> The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide meterials (MX2) (M = Mo, W; X = S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials (except WTe2) in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of those MX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthreshold slope of 150 µA/µm and 4 mV/dec, respectively. However, only the MoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.

研究员:Ram Krishna Ghosh (2013)

独立双栅极(IDG)金属氧化物半导体场效应晶体管(MOSFET)由于具有动态调节阈值电压和跨导的能力，近年来受到了广泛的关注。由于静电的不对称性质，与对称双栅晶体管相比，开发这种器件的高效紧凑模型是一项艰巨的任务。本文试图针对这方面的一些问题提出解决方案。通过求解一维泊松方程(PE)对长通道电势进行建模是开发基于表面电势的此类晶体管核心紧凑模型的最基本步骤。以往严格求解长通道非对称独立双栅极晶体管一维泊松方程的方法，得到的势模型涉及多个相互耦合的隐式方程。由于这些方程需要自洽求解，这种潜在模型对于紧凑建模显然是低效的。这项工作报告了一种不同的解决同一泊松方程的严格技术，通过它可以获得涉及单个隐式方程的广义独立双栅晶体管的电位剖面。所提出的泊松解决方案在电路仿真计算效率上至少比以前的解决方案高5倍。开发高效的终端收费模型是迈向紧凑建模的另一个关键步骤。在这项工作中，我们展示了传统的电荷线性化技术在模拟IDG mosfet的终端电荷时的局限性。 We propose a new charge linearization technique in order to model the terminal charges and transcapacitances of the IDG MOSFETs. We report two different types of quasi-static large signal models for the long channel device. In the first type, the terminal charges are expressed as closed form functions of source and drain end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on quadratic spline collocation technique and requires the input voltage equation to be solved two more times apart from the source and drain end. Proposed model has been successfully implemented in professional circuit simulator. Voltage controlled oscillators (VCOs) based on metal oxide semiconductor (MOS) varactors have become an integral part of RF communication circuits. An independently controlled double gate based MOS capacitor can bring out new functionalities, which could be interesting for RF circuit applications. For the first time, this work, explores the characteristics of MOS capacitor controlled by independent double gates by numerical simulation and analytical modeling for its possible use in RF circuit design as a varactor. By numerical simulation it is shown how the quasi-static and non-quasi-static characteristics of the first gate capacitance could be tuned by the second gate biases. Analytical solution of complete (considering both electron and hole concentration) Poisson equation (PE) is proposed. A new set of input voltage equations (IVEs) for independent double gate MOSFET are proposed by solving the governing bipolar Poisson equation rigorously. The proposed IVEs, involve the Legendre’s incomplete elliptic integral of the first kind andJacobian elliptic functions and are valid from accumulation to inversion regimes. As Legendre’s incomplete elliptic integral of first kind and Jacobian elliptic functions are computationally expensive, hence I also propose a semi-empirical solution using previous analytical solution of the PE for IDG MOS capacitor considering only electron/hole. Proposed models, which are valid from accumulation to inversion, are shown to have excellent agreement with numerical simulation for practical bias conditions.

研究员:Pankaj Kumar Thakur (2013)

在过去的40年里，对摩尔定律晶体管缩放的不懈关注提供了不断增长的晶体管性能和密度。为了继续将技术扩展到22nm节点以上，很明显，传统的大块mosfet需要被新的器件架构所取代，最有希望的是多门mosfet mufet)。英特尔在2011年年中宣布在其下一代IvyBridge微处理器的22nm高容量逻辑工艺中使用批量三门finfet。预计很快其他半导体公司也将采用muget器件。与大体积MOSFET一样，精确且物理紧凑的模型对于基于mufet的电路设计至关重要。平面双栅MOSFET (DGFET)的紧凑建模工作始于90年代末，因为它是人们可以为mufet器件设想的最简单的结构。目前为DG mosfet提出的模型适用于共用栅极对称的DG (SDG) mosfet，其中两个栅极具有相同的氧化厚度。然而，对于实际的纳米级器件，由于工艺变化和不确定性，栅极氧化物厚度之间总是存在一定程度的不对称，这可能会显著影响器件性能。与此同时，独立控制DG (IDG) mosfet因其动态调节阈值电压和跨导的能力而受到广泛关注。由于静电的不对称性质，开发高效紧凑的非对称/独立DG MOSFET模型是一项艰巨的任务。 In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two configurations 1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG (IDG) MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate (DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demon- strate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

研究人员:J. Srivatsava (2013)

尽管CMOS(互补金属氧化物半导体)技术的扩展预计还将持续10年，但需要新的技术解决方案来克服癸量计MOS晶体管的基本限制。单电子晶体管(SET)因其独特的库仑封锁振荡特性、超低功耗和纳米尺度的特征尺寸而备受关注。尽管潜力巨大，但由于一些固有的限制(例如，非常低的电流驱动)，SET很难与CMOS的大规模基础设施、经过验证的设计方法和经济可预测性进行正面竞争。然而，SET和MOS晶体管的特性是互补的。SET提倡低功耗和新功能(与库仑封锁振荡有关)，而CMOS具有高速驱动和电压增益等优势，可以弥补SET的内在缺点。因此，虽然单电子器件完全取代CMOS在不久的将来是不可能的，但将SET和CMOS结合起来可以带来纯CMOS技术无法反映的新功能。随着CMOS和SET的杂交越来越受欢迎，硅SET在与CMOS的可能集成方面似乎比金属SET更有前途。集合通常是在经典的正统理论的基础上研究的，其中岛上的能量态的量子化完全被忽略了。尽管这一假设极大地简化了所涉及的物理过程，但只有当SET是由金属岛构成时，这一假设才成立。由于半导体孤岛中能量态的量子化是不可忽视的，因此研究能量量子化对CMOS-SET混合集成电路的影响就显得尤为重要。 The main objective of this thesis is to understand energy quantization effects on SET by numerical simulations, develop simple analytical models that can capture the energy quantization effects, analyze the effects of energy quantization on SET logic inverter, and finally, develop a CAD framework for CMOS-SET co-simulation and to study the effect on energy quantization on hybrid circuits using that framework. In this work the widely accepted SIMON Monte Carlo (MC) simulator for single electron devices and circuits is used to study the effect of energy quantization. So far SIMON has been used to study SETs having metallic island. In this work, for the first time, we have shown how one can use SIMON to analyze SET island properties having discrete energy states. It is shown that energy quantization mainly changes the Coulomb Blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET logic inverter. A new model for the noise margin of SET inverter is proposed, which includes the energy quantization term. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as “Quantization Threshold”) that an SET inverter logic circuit can withstand before its noise margin falls below a specified tolerance level. It is found that SET inverter designed with CT : CG = 0.366 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization. Then the effects of energy quantization are studied for Current biased SET (CBS), which is an integral part of almost all hybrid CMOS-SET circuits. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics though it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: Negative Differential Resistance (NDR) and Neurone Cell, which use CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. A novel CAD framework is then developed for CMOS-SET co-simulation, which uses MC simulator for SET devices along with conventional SPICE. Using this framework, the effects of energy quantization are studied for some hybrid circuits, namely, SETMOS, multiband voltage filter, and multiple valued logic circuits. It is found that energy quantization degrades the performance of hybrid circuit, which could be compensated by properly tuning the bias current of SET devices. Though this study is primarily done by exhaustive MC simulation, effort has also been put to develop first order compact model for SET that includes energy quantization effects. Finally it is demonstrated that one can predict the SET behavior under energy quantization with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

研究者:Surya Shankar Dan (2009)